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1. general description the 74vhc595-q100; 74vhct595-q100 are high -speed si-gate cmos devices and are pin compatible with low-power schottky ttl (l sttl). it is specified in compliance with jedec standard no. 7a. the 74vhc595-q100; 74vhct595-q100 are 8-stage serial shift registers with a storage register and 3-state outputs. the shift registers have separate clocks. data is shifted on the positive-going transiti ons of the shift register clock input (shcp). the data in each register is transferred to the storage register on a positive-going transition of the storage register clock input (stcp). if both clocks are connected together, the shift register is always one clock pulse ahead of the storage register. the shift register has a serial input (ds) and a serial standard output (q7s) for cascading. it is also provided with asynchronous reset (active low) for all 8 shift register stages. the storage register has 8 parallel 3-state bus driv er outputs. data in the storage register appears at the output wheneve r the output enable input (oe ) is low. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? balanced propagation delays ? all inputs have schmitt-trigger action ? inputs accept voltages higher than v cc ? input levels: ? the 74vhc595-q100 operates with cmos input level ? the 74vhct595-q100 operates with ttl input level ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial-out or parallel-out shift register with output latches rev. 1 ? 15 november 2013 product data sheet
74vhc_vhct595_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 15 november 2013 2 of 21 nxp semiconductors 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial -out or parallel-out shift register with output latches 3. applications ? serial-to-parallel data conversion ? remote control holding register 4. ordering information 5. functional diagram table 1. ordering information type number package temperature range name description version 74vhc595d-q100 ? 40 ? c to +125 ? c so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 74vhct595d-q100 74VHC595PW-Q100 ? 40 ? c to +125 ? c tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 74vhct595pw-q100 74vhc595bq-q100 ? 40 ? c to +125 ? c dhvqfn16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 ? 3.5 ? 0.85 mm sot763-1 74vhct595bq-q100 fig 1. functional diagram mna554 3-state outputs 8-bit storage register 8-stage shift register q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 q 7 s 14 151 234567 9 d s sh cp st cp oe 11 10 12 13 mr
74vhc_vhct595_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 15 november 2013 3 of 21 nxp semiconductors 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial -out or parallel-out shift register with output latches fig 2. logic symbol fig 3. iec logic symbol oe mr 9 15 1 2 3 4 5 6 7 1310 14 11 12 mna552 q 1 q 0 q 2 q 3 q 4 q 5 q 6 q 7 q 7 s d s st cp sh cp mna553 15 9 1 2 3 4 5 6 7 1d 2d c1/ 10 11 14 c2 12 13 en3 srg8 r 3 fig 4. logic diagram stage 0 stages 1 to 6 stage 7 ff0 d cp q r latch d cp q ff7 d cp q r latch d cp q mna555 dq q 1 q 2 q 3 q 4 q 5 q 6 q 7 q 7 s q 0 d s st cp sh cp oe mr
74vhc_vhct595_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 15 november 2013 4 of 21 nxp semiconductors 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial -out or parallel-out shift register with output latches 6. pinning information 6.1 pinning 6.2 pin description (1) this is not a supply pin. the substrate is attached to this pad using conductive die atta ch material. there is no electrical or mechanical requi rement to solder this pad. however, if it is soldered, the solder land should remain floating or be connected to gnd. fig 5. pin configuration so16 and tssop16 fig 6. pin configuration dhvqfn16 9+&4 9+&74 4 9 & & 4 4 4 ' 6 4 2 ( 4 67&3 4 6+&3 4 0 5 *1' 46 ddd ddd 9+&4 9+&74 4 05 4 6+&3 4 67&3 4 2( 4 '6 4 4 *1' 46 4 9 && 7udqvsduhqwwrsylhz whuplqdo lqgh[duhd *1' table 2. pin description symbol pin description q1 1 parallel data output 1 q2 2 parallel data output 2 q3 3 parallel data output 3 q4 4 parallel data output 4 q5 5 parallel data output 5 q6 6 parallel data output 6 q7 7 parallel data output 7 gnd 8 ground (0 v) q7s 9 serial data output mr 10 master reset (active low) shcp 11 shift register clock input stcp 12 storage register clock input oe 13 output enable input (active low) ds 14 serial data input q0 15 parallel data output 0 v cc 16 supply voltage
74vhc_vhct595_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 15 november 2013 5 of 21 nxp semiconductors 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial -out or parallel-out shift register with output latches 7. functional description [1] h = high voltage state; l = low voltage state; ? = low-to-high transition; x = don?t care; nc = no change; z = high-impedance off-state. table 3. function table [1] control input output function shcp stcp oe mr ds q7s qn x x l l x l nc a low-level on mr only affects the shift registers x ? l l x l l empty shift register loaded into storage register x x h l x l z shift register clear; parallel outputs in high-impedance off-state ? x l h h q6s nc logic high-level shifted into shift register stage 0. contents of all shift register stages shifted through , e.g. previous state of stage 6 (internal q6s) appears on the serial output (q7s). x ? l h x nc qns contents of shift register stages (internal qns) are transferred to the storage register and parallel output stages ?? l h x q6s qns contents of shift register shifted through; previous contents of the shift register is transferred to t he storage register and the parallel output stages fig 7. timing diagram shcp ds stcp mr oe q0 q1 q6 q7 q7s z-state z-state z-state z-state mna556
74vhc_vhct595_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 15 november 2013 6 of 21 nxp semiconductors 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial -out or parallel-out shift register with output latches 8. limiting values [1] the input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] for so16 packages: above 70 ? c the value of p tot derates linearly at 8 mw/k. for tssop16 packages: above 60 ? c the value of p tot derates linearly at 5.5 mw/k. for dhvqfn16 packages: above 60 ? c the value of p tot derates linearly at 4.5 mw/k. 9. recommended operating conditions table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +7.0 v v i input voltage ? 0.5 +7.0 v i ik input clamping current v i < ? 0.5 v [1] ? 20 - ma i ok output clamping current v o < ? 0.5 v or v o >v cc +0.5v [1] ? 20 +20 ma i o output current v o = ? 0.5 v to (v cc +0.5v) ? 25 +25 ma i cc supply current - +75 ma i gnd ground current ? 75 - ma t stg storage temperature ? 65 +150 ?c p tot total power dissipation t amb = ? 40 ? c to +125 ?c [2] - 500 mw table 5. operating conditions symbol parameter conditions min typ max unit 74vhc595-q100 v cc supply voltage 2.0 5.0 5.5 v v i input voltage 0 - 5.5 v v o output voltage 0 - v cc v t amb ambient temperature ? 40 +25 +125 ?c ? t/ ? v input transition rise and fall rate v cc = 3.0 v to 3.6 v - - 100 ns/v v cc = 4.5 v to 5.5 v - - 20 ns/v 74vhct595-q100 v cc supply voltage 4.5 5.0 5.5 v v i input voltage 0 - 5.5 v v o output voltage 0 - v cc v t amb ambient temperature ? 40 +25 +125 ?c ? t/ ? v input transition rise and fall rate v cc = 4.5 v to 5.5 v - - 20 ns/v
74vhc_vhct595_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 15 november 2013 7 of 21 nxp semiconductors 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial -out or parallel-out shift register with output latches 10. static characteristics table 6. static characteristics at recommended operating conditions; voltag es are referenced to gnd (ground = 0 v). symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ max min max min max 74vhc595-q100 v ih high-level input voltage v cc = 2.0 v 1.5 - - 1.5 - 1.5 - v v cc = 3.0 v 2.1 - - 2.1 - 2.1 - v v cc = 5.5 v 3.85 - - 3.85 - 3.85 - v v il low-level input voltage v cc = 2.0 v - - 0.5 - 0.5 - 0.5 v v cc = 3.0 v - - 0.9 - 0.9 - 0.9 v v cc = 5.5 v - - 1.65 - 1.65 - 1.65 v v oh high-level output voltage v i = v ih or v il i o = ? 50 ? a; v cc = 2.0 v 1.9 2.0 - 1.9 - 1.9 - v i o = ? 50 ? a; v cc = 3.0 v 2.9 3.0 - 2.9 - 2.9 - v i o = ? 50 ? a; v cc = 4.5 v 4.4 4.5 - 4.4 - 4.4 - v i o = ? 4.0 ma; v cc = 3.0 v 2.58 - - 2.48 - 2.40 - v i o = ? 8.0 ma; v cc = 4.5 v 3.94 - - 3.80 - 3.70 - v v ol low-level output voltage v i = v ih or v il i o = 50 ? a; v cc = 2.0 v - 0 0.1 - 0.1 - 0.1 v i o = 50 ? a; v cc = 3.0 v - 0 0.1 - 0.1 - 0.1 v i o = 50 ? a; v cc = 4.5 v - 0 0.1 - 0.1 - 0.1 v i o = 4.0 ma; v cc = 3.0 v - - 0.36 - 0.44 - 0.55 v i o = 8.0 ma; v cc = 4.5 v - - 0.36 - 0.44 - 0.55 v i i input leakage current v i = 5.5 v or gnd; v cc =0vto5.5v - - 0.1 - 1.0 - 2.0 ? a i oz off-state output current v i =v ih or v il ; v o =v cc or gnd; v cc =5.5v -- ? 0.25 - ? 2.5 - ? 10 ? a i cc supply current v i =v cc or gnd; i o = 0 a; v cc =5.5v --4.0 - 40 - 80 ? a c i input capacitance - 3 10 - 10 - 10 pf 74vhct595-q100 v ih high-level input voltage v cc = 4.5 v to 5.5 v 2.0 - - 2.0 - 2.0 - v v il low-level input voltage v cc = 4.5 v to 5.5 v - - 0.8 - 0.8 - 0.8 v v oh high-level output voltage v i = v ih or v il ; v cc = 4.5 v i o = ? 50 ? a 4.4 4.5 - 4.4 - 4.4 - v i o = ? 8.0 ma 3.94 - - 3.80 - 3.70 - v v ol low-level output voltage v i = v ih or v il ; v cc = 4.5 v i o = 50 ? a - 0 0.1 - 0.1 - 0.1 v i o = 8.0 ma - - 0.36 - 0.44 - 0.55 v
74vhc_vhct595_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 15 november 2013 8 of 21 nxp semiconductors 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial -out or parallel-out shift register with output latches 11. dynamic characteristics i i input leakage current v i = 5.5 v or gnd; v cc =0vto5.5v - - 0.1 - 1.0 - 2.0 ? a i oz off-state output current v i =v ih or v il ; v o =v cc or gnd per input pin; other inputs at v cc or gnd; i o =0 a; v cc =5.5v -- ? 0.25 - ? 2.5 - ? 10 ? a i cc supply current v i =v cc or gnd; i o = 0 a; v cc =5.5v --4.0 - 40 - 80 ? a ? i cc additional supply current per input pin; v i =v cc ? 2.1 v; other inputs at v cc or gnd; i o =0 a; v cc = 4.5 v to 5.5 v - - 1.35 - 1.5 - 1.5 ma c i input capacitance - 3 10 - 10 - 10 pf table 6. static characteristics ?continued at recommended operating conditions; voltag es are referenced to gnd (ground = 0 v). symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ max min max min max table 7. dynamic characteristics voltages are referenced to gnd (groun d = 0 v); for test circuit, see figure 13 . symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max min max 74vhc595-q100 t pd propagation delay shcp to q7s; see figure 8 [2] v cc = 3.0 v to 3.6 v c l = 15 pf - 5.7 13.0 1.0 15.0 1.0 16.5 ns c l = 50 pf - 7.7 16.5 1.0 18.5 1.0 20.1 ns v cc = 4.5 v to 5.5 v c l = 15 pf - 4.0 8.2 1.0 9.4 1.0 10.5 ns c l = 50 pf - 5.4 10.0 1.0 11.4 1.0 12.5 ns stcp to qn; see figure 9 [2] v cc = 3.0 v to 3.6 v c l = 15 pf - 5.9 11.9 1.0 13.5 1.0 15.0 ns c l = 50 pf - 7.7 15.4 1.0 17.0 1.0 18.5 ns v cc = 4.5 v to 5.5 v c l = 15 pf - 4.2 7.4 1.0 8.5 1.0 9.5 ns c l = 50 pf - 5.5 9.0 1.0 10.5 1.0 11.5 ns mr to q7s; see figure 11 [3] v cc = 3.0 v to 3.6 v c l = 15 pf - 5.9 12.8 1.0 13.7 1.0 15.0 ns c l = 50 pf - 7.4 16.3 1.0 17.2 1.0 18.7 ns v cc = 4.5 v to 5.5 v c l = 15 pf - 4.4 8.0 1.0 9.1 1.0 10.0 ns c l = 50 pf - 5.6 10.0 1.0 11.1 1.0 12.0 ns
74vhc_vhct595_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 15 november 2013 9 of 21 nxp semiconductors 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial -out or parallel-out shift register with output latches t en enable time oe to qn; see figure 12 [4] v cc = 3.0 v to 3.6 v c l = 15 pf - 5.6 11.5 1.0 13.5 1.0 15.0 ns c l = 50 pf - 7.4 15.0 1.0 17.0 1.0 18.5 ns v cc = 4.5 v to 5.5 v c l = 15 pf - 4.0 8.6 1.0 10.0 1.0 11.0 ns c l = 50 pf - 5.3 10.6 1.0 12.0 1.0 13.0 ns t dis disable time oe to qn; see figure 12 [5] v cc = 3.0 v to 3.6 v c l = 15 pf - 5.4 11.0 1.0 13.0 1.0 14.5 ns c l = 50 pf - 8.7 15.7 1.0 16.2 1.0 17.5 ns v cc = 4.5 v to 5.5 v c l = 15 pf - 3.8 8.0 1.0 9.5 1.0 10.5 ns c l = 50 pf - 5.8 10.3 1.0 11.0 1.0 12.0 ns f max maximum frequency shcp or stcp; see figure 8 and 9 v cc = 3.0 v to 3.6 v 80 125 - 60 - 40 - mhz v cc = 4.5 v to 5.5 v 130 170 - 110 - 90 - mhz t w pulse width shcp high or low; see figure 8 v cc = 3.0 v to 3.6 v 5.0 - - 5.0 - 5.0 - ns v cc = 4.5 v to 5.5 v 5.0 - - 5.0 - 5.0 - ns stcp high or low; see figure 9 v cc = 3.0 v to 3.6 v 5.0 - - 5.0 - 5.0 - ns v cc = 4.5 v to 5.5 v 5.0 - - 5.0 - 5.0 - ns mr low; see figure 11 v cc = 3.0 v to 3.6 v 5.0 - - 5.0 - 5.0 - ns v cc = 4.5 v to 5.5 v 5.0 - - 5.0 - 5.0 - ns t su set-up time ds to shcp; see figure 9 v cc = 3.0 v to 3.6 v 3.5 - - 3.5 - 3.5 - ns v cc = 4.5 v to 5.5 v 3.0 - - 3.0 - 3.0 - ns shcp to stcp; see figure 10 v cc = 3.0 v to 3.6 v 8.5 - - 8.5 - 8.5 - ns v cc = 4.5 v to 5.5 v 5.0 - - 5.0 - 5.0 - ns t h hold time ds to shcp; see figure 10 v cc = 3.0 v to 3.6 v 1.5 - - 1.5 - 1.5 - ns v cc = 4.5 v to 5.5 v 2.0 - - 2.0 - 2.0 - ns table 7. dynamic characteristics ?continued voltages are referenced to gnd (groun d = 0 v); for test circuit, see figure 13 . symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max min max
74vhc_vhct595_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 15 november 2013 10 of 21 nxp semiconductors 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial -out or parallel-out shift register with output latches t rec recovery time mr to shcp; see figure 11 v cc = 3.0 v to 3.6 v 3.0 - - 3.0 - 3.0 - ns v cc = 4.5 v to 5.5 v 2.5 - - 2.5 - 2.5 - ns c pd power dissipation capacitance f i = 1 mhz; v i =gndtov cc [6] [7] -180- - - - - pf 74vhct595-q100; v cc = 4.5 v to 5.5 v t pd propagation delay shcp to q7s; see figure 8 [2] c l = 15 pf - 3.8 8.2 1.0 9.0 1.0 10.0 ns c l = 50 pf - 5.2 10.0 1.0 11.0 1.0 12.0 ns stcp to qn; see figure 9 [2] c l = 15 pf - 4.0 7.4 1.0 8.5 1.0 9.5 ns c l = 50 pf - 5.3 9.0 1.0 10.5 1.0 11.5 ns mr to q7s; see figure 11 [3] c l = 15 pf - 4.6 8.2 1.0 9.5 1.0 10.5 ns c l = 50 pf - 5.8 10.5 1.0 11.5 1.0 12.5 ns t en enable time oe to qn; see figure 12 [4] c l = 15 pf - 4.8 9.0 1.0 11.0 1.0 12.0 ns c l = 50 pf - 6.2 11.6 1.0 13.0 1.0 14.5 ns t dis disable time oe to qn; see figure 12 [5] c l = 15 pf - 3.6 6.9 1.0 8.0 1.0 9.0 ns c l = 50 pf - 5.8 10.3 1.0 11.0 1.0 12.0 ns f max maximum frequency shcp and stcp; see figure 8 and 9 130 170 - 110 - 90 - mhz t w pulse width shcp high or low; see figure 8 5.0 - - 5.0 - 5.0 - ns stcp high or low; see figure 9 5.0 - - 5.0 - 5.0 - ns mr low; see figure 11 5.0 - - 5.0 - 5.0 - ns t su set-up time ds to shcp; see figure 9 3.0 - - 3.0 - 3.0 - ns shcp to stcp; see figure 10 5.0 - - 5.0 - 5.0 - ns t h hold time ds to shcp; see figure 10 2.0 - - 2.0 - 2.0 - ns t rec recovery time mr to shcp; see figure 11 3.0 - - 3.0 - 3.0 - ns table 7. dynamic characteristics ?continued voltages are referenced to gnd (groun d = 0 v); for test circuit, see figure 13 . symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max min max
74vhc_vhct595_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 15 november 2013 11 of 21 nxp semiconductors 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial -out or parallel-out shift register with output latches [1] typical values are measured at nominal supply voltage. [2] t pd is the same as t phl and t plh . [3] t pd is the same as t phl only. [4] t en is the same as t pzl and t pzh . [5] t dis is the same as t plz and t phz . [6] c pd is used to determine the dynamic power dissipation (p d in ? w). p d =c pd ? v cc 2 ? f i + ? (c l ? v cc 2 ? f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; ? (c l ? v cc 2 ? f o ) = sum of outputs; c l = output load capacitance in pf; v cc = supply voltage in v. [7] all 9 outputs switching. 12. waveforms c pd power dissipation capacitance f i = 1 mhz; v i =gndtov cc [6] [7] -190- - - - - pf table 7. dynamic characteristics ?continued voltages are referenced to gnd (groun d = 0 v); for test circuit, see figure 13 . symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max min max measurement points are given in table 8 . v ol and v oh are typical output voltage levels that occur with the output load. fig 8. shift clock pulse, maximum frequency and input to output propagation delays mna557 sh cp input q 7 s output t plh t phl t w 1/f max v m v oh v i gnd v ol v m
74vhc_vhct595_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 15 november 2013 12 of 21 nxp semiconductors 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial -out or parallel-out shift register with output latches measurement points are given in table 8 . v ol and v oh are typical output voltage levels that occur with the output load. fig 9. storage clock to output propagation delays mna558 st cp input q n output t plh t phl t w t su 1/f max v m v oh v i gnd v ol v m sh cp input v i gnd v m measurement points are given in table 8 . the shaded areas indicate when the input is per mitted to change for predictable output performance. v ol and v oh are typical output voltage levels that occur with the output load. fig 10. data set-up and hold times mna560 gnd gnd t h t su t h t su v m v m v m v i v oh v ol v i q 7 s output sh cp input d s input
74vhc_vhct595_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 15 november 2013 13 of 21 nxp semiconductors 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial -out or parallel-out shift register with output latches measurement points are given in table 8 . v ol and v oh are typical output voltage levels that occur with the output load. fig 11. master reset to output propagation delays mna561 mr input sh cp input q 7 s output t phl t w t rec v m v oh v ol v i gnd v i gnd v m v m measurement points are given in table 8 . v ol and v oh are typical output voltage levels that occur with the output load. fig 12. enable and disable times mna450 t plz t phz outputs disabled outputs enabled v oh ? 0.3 v v ol + 0.3 v outputs enabled output low-to-off off-to-low output high-to-off off-to-high oe input v i v cc v m v ol v oh gnd gnd t pzl t pzh v m v m table 8. measurement points type input output v m v m 74vhc595-q100 0.5v cc 0.5v cc 74vhct595-q100 1.5 v 0.5v cc
74vhc_vhct595_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 15 november 2013 14 of 21 nxp semiconductors 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial -out or parallel-out shift register with output latches test data is given in table 9 . definitions for test circuit: c l = load capacitance including jig and probe capacitance. r l = load resistance. r t = termination resistance should be equal to the output impedance z o of the pulse generator. s1 = test selection switch. fig 13. load circuitry for switching times v m v m t w t w 10 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % t f t r t r t f 001aad983 dut v cc v cc v i v o r t r l s1 c l open g table 9. test data type input load s1 position v i t r , t f c l r l t phl , t plh t pzh , t phz t pzl , t plz 74vhc595-q100 v cc ? 3.0ns 15pf, 50pf 1k ? open gnd v cc 74vhct595-q100 3.0 v ? 3.0ns 15pf, 50pf 1k ? open gnd v cc
74vhc_vhct595_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 15 november 2013 15 of 21 nxp semiconductors 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial -out or parallel-out shift register with output latches 13. package outline fig 14. package outline sot109-1 (so16) x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot109-1 99-12-27 03-02-19 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
74vhc_vhct595_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 15 november 2013 16 of 21 nxp semiconductors 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial -out or parallel-out shift register with output latches fig 15. package outline sot403-1 (tssop16) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.1 pin 1 index
74vhc_vhct595_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 15 november 2013 17 of 21 nxp semiconductors 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial -out or parallel-out shift register with output latches fig 16. package outline sot763-1 (dhvqfn16) terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 3.6 3.4 d h 2.15 1.85 y 1 2.6 2.4 1.15 0.85 e 1 2.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot763-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot763-1 dhvqfn16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 27 15 10 9 8 1 16 x d e c b a terminal 1 index area ac c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) 02-10-17 03-01-27
74vhc_vhct595_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 15 november 2013 18 of 21 nxp semiconductors 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial -out or parallel-out shift register with output latches 14. abbreviations 15. revision history table 10. abbreviations acronym description cmos complementary metal-oxide semiconductor esd electrostatic discharge hbm human body model mil military mm machine model ttl transistor-transistor logic table 11. revision history document id release date data sheet status change notice supersedes 74vhc_vhct595_q100 v.1 20131115 product data sheet - -
74vhc_vhct595_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 15 november 2013 19 of 21 nxp semiconductors 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial -out or parallel-out shift register with output latches 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 16.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 16.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qualified for use in automotive applications. unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74vhc_vhct595_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 15 november 2013 20 of 21 nxp semiconductors 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial -out or parallel-out shift register with output latches no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 16.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 17. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74vhc595-q100; 74vhct595-q100 8-bit serial-in/serial -out or parallel-out shift register with output latches ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 15 november 2013 document identifier: 74vhc_vhct595_q100 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 5 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 recommended operating conditions. . . . . . . . 6 10 static characteristics. . . . . . . . . . . . . . . . . . . . . 7 11 dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 19 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 16.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 16.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 17 contact information. . . . . . . . . . . . . . . . . . . . . 20 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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